In typical circuit design, circuit components are arranged to optimize space and/or circuit performance. Such arrangements can include the “layout” or pattern definition of each of the layers used in a semiconductor manufacturing process. For example, such layout can include metal interconnect or connectivity layers that are converted to masks or reticles for use in a wafer fabrication facility that manufactures ICs (i.e., “chips”).
While some circuits are designed using “custom” layout, others are designed using a partially or fully automated design flow. Application-Specific Integrated Circuit (ASIC) designs, as well as other functional blocks within a larger chip, such as System-On-Chip (SOC) designs, may employ custom and/or ASIC type flows on the same chip. In any event, typical ASIC flows use “place-and-route” tools for placing logic or circuit “blocks” and then “routing” or connecting the interface signals between the blocks. Such routing between circuit blocks is typically done using one or more metal connectivity layers.
Referring now to FIG. 1A, a conventional connection layer cross section diagram is shown and indicated by the general reference character 100. The five metal layers shown include metal-1 (M1) 102, metal-2 (M2) 106, metal-3 (M3) 110, metal-4 (M4) 114, and metal-5 (M5) 118. Dielectric 104 isolates the M1 connectivity layer, dielectric 108 isolates the M2 connectivity layer, dielectric 112 isolates the M3 connectivity layer, dielectric 116 isolates the M4 connectivity layer, and dielectric 120 isolates the M5 connectivity layer. In FIG. 1B, layer-to-layer connections associated with the diagram of FIG. 1A are shown and indicated by the general reference character 150. In FIG. 1B, contact (C) 152 connects M1 to a layer below, via-1 (V1) 154 connects M2 to M1, via-2 (V2) 156 connects M3 to M2, via-3 (V3) 158 connects M4 to M3, and via-4 (V4) 160 connects M5 to M4. In conventional automated signal path routing approaches, either certain connectivity layers are strictly designated for specific signal categories (e.g., M5 for power signal routing, M4 for clock signals, etc.) to restrict routing choices, or the routing is randomized with respect to the connectivity layer so as to emphasize minimized layout area.
However, such conventional approaches to automated signal path routing are typically not optimized for power consumption or signal integrity concerns. Limitations of such conventional approaches result from the routing not being done with sufficient consideration of the “capacitivity” (i.e., capacitance per unit length or area) and the switching activity of the signal path. Accordingly, a signal path routing using a conventional approach may not minimize the capacitivity for a high switching activity signal.
Given the increasing demands on circuit designers to create chips of increasing density, decreasing wire and transistor widths, and decreasing power supply and power consumption, it is difficult to ensure optimal signal path routing in a manner that also takes steps to minimize power consumption, particularly in an automated routing flow. Increasing the complexity, flexibility and/or functionality of the circuitry on a chip exacerbates these challenges. Thus, what is needed is a tool with which integrated circuit designers can automatically optimize signal path routing so as to reduce power consumption and increase signal integrity.